What was written here is still true. We squeezed all in a DIL-28 formfactor and improved the documentation (Gerberfiles). So this is one of our new Building Blocks for anything which needs a stable 100 MHz Reference Clock, locked to a stable 10 MHz Reference Clock.

Specifications :

INPUT FREQUENCY	10 MHz
OUTPUT FREQUENCY	100 MHz
MIN INPUT LEVEL	tbd
MAX INPUT LEVEL	20 dBm
SUPPLY	+ 5 V ... 35 V approx. 12 mA

Instead of a Block-Diagram. The 10 MHz input is at Pin 28, from which it passes a limiter (BAV99, D1). It is then ac-coupled to the HMC1031 (0.1 MHz to 500 MHz Clock Generator with Integer N PLL). This PLL controls a VCXO (ABLNO-V-100.000MHz-T2, Ultra Low Phase Noise XO / VCXO). Power Input is at Pin 1. As there was no space left, a decoupling capacitor must be put externally. Yes, as close to the pin as possible.

The performace is similiar to commercial devices. Once more it must be noted, that the 10 MHz used to lock this thing must be of the best possible quality. What ever garbage rides on the 10 MHz can be seen in the output - multiplied by ten !

As cmos oscillators are rich in harmonics it is also possible to filter out one of them, maybe to clock a dds or as a (clean) lo source.

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